Semiconductor wafers are often provided with a layer produced by means of vapor deposition. The semiconductor wafer is usually held by a rotating susceptor during the deposition of the layer, said susceptor being arranged in a process chamber. Upper and lower covers (domes) form boundaries of the process chamber which are transmissive to thermal radiation and through which radiation energy is transmitted into the process chamber and onto the semiconductor wafer. Process chambers for vapor deposition have been described for instance in U.S. Pat. No. 5,487,358 and US 2013/0078743 A1.
The semiconductor wafer is heated to a specific temperature that is optimal for the deposition of the layer. The process chamber furthermore has on the side walls connections for introducing process gas into the process chamber and for discharging process gas and gaseous products of the process gas from the process chamber. The process gas is conducted over the side area of the semiconductor wafer that is to be coated. Upon contact with the semiconductor wafer heated to deposition temperature, process gas is decomposed and the desired layer is deposited on the semiconductor wafer.
Epitaxial deposition processes are disclosed for example in U.S. Pat. Nos. 5,904,769A, 6,110,290A and EP 1 042 544 B1.
In order to fulfill the continuously increasing quality requirements, the uniform deposition of the deposited layer on one side of the semiconductor wafer is required. The uniformity of the deposited layer and therefore the geometry of the wafer surface is negatively affected for instance by inhomogeneous gas flows due to turbulences within the reaction chamber. Such turbulences may occur due to deposits on inner parts of the reaction chamber, for example on parts of the susceptor, the inner surface of the upper cover or the inner side of the side walls.
In order to avoid such an inhomogeneous gas flow, U.S. Pat. No. 6,013,319 discloses the placement of one or more baffles within the reaction chamber in order to reduce gas flow turbulences and correspondingly reduce epitaxial layer thickness variations during processing resulting in a better flatness and layer thickness control. However, the surface of the baffles can also be affected by deposits resulting in changes of the flow situation within the reaction chamber.
Because it is not possible to completely prevent depositing of products of the process gas in the interior of the process chamber, it is necessary to clean the process chamber at specific intervals. Cleaning is effected by means of vapor phase etching, for example.
Semiconductor wafers cannot be coated during the cleaning of the process chamber. Therefore, there is a great interest in having to carry out the cleaning of the process chamber as infrequently as possible.
For this reason, EP 0 808 917 A1 recommends controlling the temperature of the walls of the process chamber within a narrow temperature range in a control loop. It specifically proposes cooling the process chamber by means of a cooling gas from outside and controlling the temperature of the walls by controlling the inflow of cooling gas to a target temperature.
According to US 2013/0078743 A1 the coating of the inner surface of the upper cover with products of the process gas begins temporally later in the center of the upper cover than at locations that are distant from the center of the upper cover. Hence it is therefore advantageous to measure the temperature of the upper cover in the center of the outer surface of the upper cover.